1. Field of the Invention
The invention relates to a semiconductor integrated circuit, a system board and a debugging system, and more particularly relates not only to a semiconductor integrated circuit which comprises a plurality of microprocessors mounted on a single semiconductor substrate, can monitor and control each of the microprocessors independently, and organically debug the microprocessors but also to a system board for mounting the semiconductor integrated circuit and a debugging system having the system board.
2. Description of the Related Art
Following recent improvements in a semiconductor processing technique, a system LSI (e.g. an ASIC (application specific integrated circuit)) which includes a plurality of microprocessor cores mounted on a single semiconductor substrate such as a silicon chip and is intended for a specific use has been extensively developed. Such a multi-processor is developed for the following reasons. The transaction of the system LSI is divided into a plurality of tasks. Processors which are optimum for the respective tasks are simultaneously operated. This is effective in extensively improving a data processing speed. Further, the microprocessors are mounted on the single silicon chip, which can downsize the system LSI.
A system LSI applied to a multimedia or especially a system LSI which performs image compression/extension is required to compute a great amount of data and complete to process the data on a real time basis. In order to meet these requirements, it is conceivable to provide combined hardware circuits in the system LSI, or to constitute the system LSI using a multiprocessor. The latter is popular at present as described hereinafter.
In the case of the image compression/expansion, the system LSI constituted by the multiprocessor is easy to divide the transaction into a plurality of tasks, and to process them using a pipeline technique due to dependence of information. Further, the system LSI can assign different tasks to one processor by using a time sharing system, so that it is not necessary to provide a plurality of dedicated hardware circuits. In short, the number of dedicated hardware circuits can be reduced. Still further, the system LSI is compatible with modifications of a specification or algorithm by making firmware rewritable. This means that the system LSI itself can easily improve its performance, and that a user can easily improve the performance of the system LSI.
However, the system LSI including a plurality of microprocessors mounted on the single silicon chip seems to suffer from a problem related to debugging system design. Such a problem will be described hereinafter with reference to FIG. 1 and FIG. 2 showing debugging systems 60 and 70, respectively.
Referring to FIG. 1, a debugging system 60 is usually provided not only with a serial port in order to debug microprocessors 604 and 605 but also a user target system 600 to be debugged and a debugging tool 620 to execute a debugging task. The user target system 600 includes a system LSI 601 where the microprocessors 604 and 605 are integrated, an internal memory 602 connected to the system LSI 601, and an I/O interface circuit 603.
The system LSI 601 includes the microprocessors 604 and 605, a debugging module 606, a memory controller 608, a direct memory access (DMA) controller 609 and an I/O controller 610, all of which share the internal main bus 607 and are mutually connected. The debugging module 606 is connected to the debugging tool 620 via an external debug interface 62. Each of the microprocessors 604 and 605 is provided with a processor core 611 and a bus interface unit 612. The debugging module 606 is provided with a serial I/F 613 and an exclusive control semaphore 614.
The system LSI 601 does not have a special debug support unit but can execute debug control using a debugging software program, which is supplied from the debugging tool 620 to the serial I/F 613 of the debugging module 606 via the external debug interface 62, and is visible as a memory image on the internal main bus 607. In the foregoing system LSI 601, the debugging program happens to be simply stored in an external user memory. Anyway, the exclusive control semaphore 614 is usually provided in the system LSI 601 in order to prevent collision of access to of data resources in which both the microprocessors 604 and 605 synchronously gain access to the serial port of the debugging module 606.
Referring to FIG. 1, the debugging system 60 seems to be problematic in the following respects.                (1) First of all, there is a problem of how to debug bugs caused when the microprocessors 604 and 605 synchronously gain access to the same data resource. Especially, a conflicting state of the internal main bus 607 is a very important piece of information for locating bugs, should remain as it is, and should be observed at the time of debugging. Further, debugging should be performed even when the conflicting state becomes serious and the internal main bus 607 is in deadlock.        
In the debugging system 60, a debugging software program itself is however supplied from the debugging tool 620 via the debugging module 606 and the internal main bus 607, so that the conflicting state is destroyed and cannot be observed. Precisely, the debugging program cannot be started until the internal main bus 607 is freed from the deadlock.                (2) The internal main bus 607 usually gains access only to the microprocessor 604 or 605. As a result, there is a time difference between instructions provided to the microprocessors 604 and 605, so that the microprocessors 604 and 605 may not operate synchronously. Especially when a user mode is changed to a debugging mode or when the debugging mode is changed to the user mode, it is necessary to maintain relative positions where the program should be executed in the microprocessors 604 and 605 during the transition.        
However, when the user mode is resumed after the debugging mode, only one of the microprocessors 604 and 605 is able to provide the instruction and perform memory access. It is assumed here that the microprocessor 604 is instructed to return to the user mode prior to the microprocessor 605. In this case, the microprocessors 604 and 605 receive return instructions at different times, which means that it is impossible to correctly know the relative positions to execute the debugging program.                (3) The microprocessors 604 and 605 gain access to the debugging module 606 via the internal main bus 607, which is not authorized to give the access right to only the microprocessor 604 or 605.        
The debugging program is created assuming that the microprocessors 604 and 605 impartially execute the program. Therefore, it is impossible to enable only the microprocessor 604 or 605 to continuously execute the debugging program with preference. This would reduce the execution efficiency of the debugging program.                (4) The debugging system 60 should efficiently control the microprocessors 604 and 605 in order to assure its reliable debugging performance. For this purpose, the debugging system 60 has to determine which the microprocessor 604 or 605 gains access thereto via the internal main bus 607.        
However, the microprocessors 604 and 605 cannot be independently controlled at the time of debugging. Therefore, it is necessary to selectively operate the microprocessor 604 or 605 using software which contains information peculiar to the microprocessors 604 and 605. Such a selective operation is necessary for the microprocessor 604 to be controlled, for example, but is not required at all for the other microprocessor 605.
Referring to FIG. 2, a debugging system 70 comprises microprocessors 704 and 705, and a debugging module which offers a debugging function to an external unit when either the microprocessor 704 or 705 is operated. Further, the debugging system 70 includes a user target system 700 and a debugging tool 720, similarly to the debugging system 60 shown in FIG. 1.
The user target system 700 includes a system LSI 701, an internal memory 702 connected to the system LSI 701, and an I/O interface circuit 703.
The system LSI 701 is provided with the microprocessors 704 and 705, a debugging module selector 706, a memory controller 708, a DMA controller 709, and an I/O controller 710. The circuits except for the debugging module selector 706 share the internal main bus 707 and are mutually connected. The debugging module selector 706 is connected to the debugging tool 720 via an external debug interface 72. Each of the microprocessors 704 and 705 is provided with a processor core 711, the debugging module 712, a bus interface unit 713, and a debug support unit 714.
Therefore, the foregoing system LSI 701 can offer a debugging program without using the internal main bus 707. Further, debugging functions of the microprocessors 704 and 705 can be independently controlled. The debugging system 70 can overcome the problems (1), (3) and (4) of the debugging system 60.
However, the debugging system 70 is difficult to solve the problem (2), and still seems to have the following problems.                (1) The debugging tool 720 gains access to the internal memory 720 via the internal main bus 707 in response to instructions of the microprocessor 704 or 705, which would reduce an effective transferring speed of the debugging program.        (2) In the debugging system 70, and especially in the system LSI 701, the microprocessors 704 and 705 include the debugging modules 712, respectively, which unnecessarily enlarges the system LSI 701, and increases a manufacturing cost thereof. Further, the user target system 700 and debugging system 70 would be enlarged and increase their manufacturing costs.        
In summary, the debugging system 60 in FIG. 1 has the following problems: (1-1) it is not possible to observe the conflicting state of the internal main bus 607 when the single debugging module 606 for assisting the debugging task uses the software in order to perform debugging control to the microprocessors 604 and 605 which share the internal main bus 607 of the system LSI 601; (1-2) it is impossible to accurately know the relative positional relationship of the debugging programs; (1-3) the microprocessor 604 or 605 cannot operate continuously; and (1-4) the microprocessor 604 or 605 should be selectively operated using the software which includes information peculiar to these microprocessors 604 and 605.
Further, the debugging system 70 in FIG. 2 has the problems: (2-1) it is not possible to accurately know the relative positional relationship of the debugging programs; (2-2) the effective transferring speed of the debugging programs is reduced; (2-3) the circuit configuration is inevitably enlarged; and (2-4) the manufacturing costs are increased.